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dc.contributor.authorHu, Yu-Henen_US
dc.contributor.authorChen, Sao-Jieen_US
dc.date.accessioned2007-07-13T19:24:28Z
dc.date.available2007-07-13T19:24:28Z
dc.date.issued1990en_US
dc.identifier.citationYu, H. Hen, C.S.J. (1990). Gm Plan: A Gate Matrix Layout Algorithm Based On Artificial Intelligence Planning Techniques. Ieee Transactions On Computer Aided Design Of Integrated Circuits And Systems, 9(8), 836-845.en_US
dc.identifier.urihttp://digital.library.wisc.edu/1793/9938
dc.descriptionThis material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.format.extent1080227 bytes
dc.format.mimetypeapplication/pdfen_US
dc.format.mimetypeapplication/pdf
dc.relation.ispartofhttp://www.ieee.org/en_US
dc.relation.ispartofhttp://ieeexplore.ieee.org/servlet/opac?punumber=43en_US
dc.rightsCopyright 1990 Institute of Electrical and Electronics Engineersen_US
dc.rights©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.titleGM_Plan: A gate matrix layout algorithm based on artificial intelligence planning techniquesen_US
dc.identifier.doihttp://dx.doi.org/10.1109/43.57791en_US


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