Show simple item record

dc.contributor.authorPour, Andreas Fariden_US
dc.contributor.authorHill, Mark D.en_US
dc.date.accessioned2007-07-13T19:22:29Z
dc.date.available2007-07-13T19:22:29Z
dc.date.issued1993en_US
dc.identifier.citationAndreas, P. Farid, & Hill, M. D. (1993). Performance Implications Of Tolerating Cache Faults. Ieee Transactions On Computers, 42(3), 257-267.en_US
dc.identifier.urihttp://digital.library.wisc.edu/1793/9674
dc.descriptionThis material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.format.extent970443 bytes
dc.format.mimetypeapplication/pdfen_US
dc.format.mimetypeapplication/pdf
dc.relation.ispartofhttp://www.ieee.org/en_US
dc.relation.ispartofhttp://ieeexplore.ieee.org/servlet/opac?punumber=12en_US
dc.rightsCopyright 1993 Institute of Electrical and Electronics Engineersen_US
dc.rights©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.titlePerformance implications of tolerating cache faultsen_US
dc.identifier.doihttp://dx.doi.org/10.1109/12.210168en_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record