| dc.description.abstract | An instruction is control independent of a preceding conditional branch if the decision to execute the instruction does not depend on the outcome of the branch -- this typically occurs if the
two paths following the branch re-converge prior to the control independent instruction. A speculative instruction that is control independent of an earlier predicted branch does not necessarily have to be squashed and re-executed if the branch is predicted incorrectly. Consequently, control independence has been put forward as a significant new source of instruction level parallelism in future generation processors. However, its performance potential under practical hardware constraints is not known, and even less is understood about the factors that contribute to or limit the performance of control independence.
A study of control independence in the context of superscalar processors is presented. First, important aspects of control independence are identified and singled out for study, and a series of idealized machine models are used to isolate and evaluate these aspects. It is shown that much of the performance potential of control independence is lost due to data dependences and wasted resources consumed by incorrect control dependent instructions. Even so, control independence can close the performance gap between real and perfect branch prediction by as much as half.
Next, important implementation issues are discussed and some design alternatives are given. This is followed by a more detailed set of simulations, where the key implementation features are
realistically modeled. These simulations show typical performance improvements of 10 to 30 percent over a baseline superscalar processor. | en_US |
