| dc.contributor.author | Zilles, Craig B. | en_US |
| dc.contributor.author | Sohi, Gurindar Singh | en_US |
| dc.date.accessioned | 2007-07-13T19:20:53Z | |
| dc.date.available | 2007-07-13T19:20:53Z | |
| dc.date.issued | 2000 | en_US |
| dc.identifier.citation | Zilles, C. B., & Sohi, G. S. (2000). Understanding the backward slices of performance degrading instructions. In ISCA-27: The 27th Annual International Symposium on Computer Architecture, Jun 10-Jun 14 2000, , 172-181. | en_US |
| dc.identifier.uri | http://digital.library.wisc.edu/1793/9462 | |
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| dc.format.extent | 1152145 bytes | |
| dc.format.mimetype | application/pdf | en_US |
| dc.format.mimetype | application/pdf | |
| dc.publisher | Institute of Electrical and Electronics Engineers Computer Society, Los Alamitos, CA, USA | en_US |
| dc.relation.ispartof | http://www.ieee.org/ | en_US |
| dc.relation.ispartof | http://www.acm.org/pubs/contents/proceedings/series/isca/ | en_US |
| dc.rights | Copyright 2000 Institute of Electrical and Electronics Engineers | en_US |
| dc.rights | ©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
| dc.title | Understanding the backward slices of performance degrading instructions | en_US |
