| dc.contributor.author | Sohi, Gurindar Singh | en_US |
| dc.date.accessioned | 2007-07-13T19:18:52Z | |
| dc.date.available | 2007-07-13T19:18:52Z | |
| dc.date.issued | 1990 | en_US |
| dc.identifier.citation | Sohi, G. S. (1990). Instruction Issue Logic For High Performance, Interruptible, Multiple Functional Unit, Pipelined Computers. Ieee Transactions On Computers, 39(3), 349-359. | en_US |
| dc.identifier.uri | http://digital.library.wisc.edu/1793/9196 | |
| dc.description | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | en_US |
| dc.format.extent | 1191049 bytes | |
| dc.format.mimetype | application/pdf | en_US |
| dc.format.mimetype | application/pdf | |
| dc.relation.ispartof | http://www.ieee.org/ | en_US |
| dc.relation.ispartof | http://ieeexplore.ieee.org/servlet/opac?punumber=12 | en_US |
| dc.rights | Copyright 1990 Institute of Electrical and Electronics Engineers | en_US |
| dc.rights | ©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
| dc.title | Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers | en_US |
| dc.identifier.doi | http://dx.doi.org/10.1109/12.48865 | en_US |
