Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Sohi, G. S. (1990). Instruction Issue Logic For High Performance, Interruptible, Multiple Functional Unit, Pipelined Computers. Ieee Transactions On Computers, 39(3), 349-359.