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dc.contributor.authorHu, Yu-Henen_US
dc.contributor.authorChen, Sao-Jieen_US
dc.date.accessioned2007-07-13T19:18:38Z
dc.date.available2007-07-13T19:18:38Z
dc.date.issued1989en_US
dc.identifier.citationYu, H. Hen, C.S.J. (1989). GM Plan: A gate matrix layout algorithm based on artificial intelligence planning techniques. In IEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 3, May 8-11 1989, 3, 1867-1870.en_US
dc.identifier.urihttp://digital.library.wisc.edu/1793/9164
dc.descriptionThis material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.format.extent433531 bytes
dc.format.mimetypeapplication/pdfen_US
dc.format.mimetypeapplication/pdf
dc.publisherPubl by IEEE, Piscataway, NJ, USAen_US
dc.relation.ispartofhttp://www.ieee.org/en_US
dc.relation.ispartofhttp://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000089en_US
dc.rightsCopyright 1989 Institute of Electrical and Electronics Engineersen_US
dc.rights©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.titleGM Plan: A gate matrix layout algorithm based on artificial intelligence planning techniquesen_US
dc.identifier.doihttp://dx.doi.org/10.1109/ISCAS.1989.100732en_US


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