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dc.contributor.advisorMorrow, Katherine
dc.contributor.authorChadha, Aman
dc.date.accessioned2014-07-16T19:40:02Z
dc.date.available2014-07-16T19:40:02Z
dc.date.issued2014-05-18
dc.identifier.urihttp://digital.library.wisc.edu/1793/69561
dc.description.abstractThis report documents efforts to assemble and modify a set of benchmark circuits for testing a new class of circuit partitioning algorithms designed for heterogeneous FPGAs. Often, computations can be implemented using different types of resources within these devices; the new partitioning algorithms incorporate the circuit mapping step, where computations are mapped to specific resource types, into the partitioning algorithms themselves. We elaborate on the details of this new form of partitioning called ?multi-personality? partitioning. While remapping provides a great deal of flexibility to the partitioner to modify the implementation of circuit nodes in order to meet the desired partitioning criteria, testing this new partitioner requires large, heterogeneous netlists. In this work we develop a list of requirements for the needed benchmarks, investigate existing benchmarks to determine their suitability, and document how we adapt the chosen benchmarks for use in testing multi-personality partitioning algorithms. Finally, we also discuss initial efforts in assembling and developing a set of benchmarks for testing another new form of partitioning called ?content-aware? partitioning.en
dc.subjectpartitioningen
dc.subjectmulti-personality partitioningen
dc.subjectcontent-aware partitioningen
dc.subjectbenchmarksen
dc.subjectRTLen
dc.subjectVerilogen
dc.subjectcircuit partitioningen
dc.subjectHDL benchmarksen
dc.titleBenchmark Creation for Multi-Personality and Content-Aware Circuit Partitioning Algorithmsen
dc.typeThesisen
thesis.degree.levelMSen
thesis.degree.disciplineElectrical Engineeringen


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