| dc.description.abstract | Due to limits in technology scaling, energy efficiency of logic
devices is decreasing in successive generations. To provide continued
performance improvements without increasing power, regardless
of the sequential or parallel nature of the application, microarchitectural
energy efficiency must improve. We propose Dynamically
Specialized Execution to improve the energy efficiency
of general purpose programmable processors. The key insights of
this work are the following. First, applications execute in phases
and these phases can be determined by creating a path-tree of
basic-blocks rooted at the inner-most loop. Second, specialized
datapaths corresponding to these path-trees can be constructed by
interconnecting a set of heterogeneous computation units with a
circuit-switched network, which we refer to as DySER blocks.
These blocks can be easily integrated with a conventional processor.
A synthesized RTL implementation using an industry 55nm
technology library shows a 64-functional-unit DySER block occupies
approximately the same area as a 64 KB single-ported SRAM
and can execute at 2 GHz. Using the GCC compiler, we identify
path-trees and evaluate the PARSEC, SPEC and Parboil benchmarks
suites, using our extensions for mapping code to DySER.
Our results show that in most cases two DySER blocks can achieve
the same performance (within 5%) as having a specialized block
for each path-tree. A 64-FU DySER block can cover 12% to 100%
of the dynamically executed instruction stream. When integrated
with a dual-issue out-of-order processor, two DySER blocks provide
geometric mean speedup of 2.1X (1.15X to 10X), and geometric
mean energy reduction of 40% (up to 70%), and 60% energy
reduction if no performance improvement is required. | en_US |
