Implementation of Complement Mode Execution
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As technology goes deeper into the submicron range device aging effects become increasingly powerful. The Colt duty cycle equalizer gives a microarchitectural solution to this problem with execution of complemented data during alternate epochs. This results in almost balanced duty cycles in the internal nodes and aging is effectively slowed down. This work adds to previous work done by Erika et al.  and presents an analytical proof of complement mode execution for addition and multiplication. We also implemented Colt on OpenSPARC T1 processor and identified the changes needed to be made in the datapath. Synthesis results from floating point addition indicate a delay penalty of 12% and an area penalty of 22.9%. In case of floating point multiplication the penalties were 10% and 11% for delay and area respectively. In addition, a gate level implementation of a 64-bit Wallace tree multiplier was also done to estimate the timing and the area penalty incurred in incorporating Colt. The results show that for a multiplier a delay penalty of 11% and an area penalty of 11.4% is incurred. The simulations were performed at 110 nm node.