Finding the Parasitic Inductances in a VLSI System Utilizing an Efficient Tree-Code Algorithm
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Area and power have become larger motivators recently than in the past in both the general purpose and ASIC environment. With the advent of sub-45 micron technologies, more transistors can be fit into a specified area, creating much more dense and complex circuitry. There has also been an increased pressure in time-to-market deadlines causing shorter product cycles. These motivators have pushed the necessity for better VLSI-level algorithms that can find the trade-offs involved with minimizing the total area of the circuit while keeping delay constrained. Most VLSI algorithms, such as those used in Cadence, focus only on finding the parasitic capacitances within a circuit, which up until recently have been the dominating forces that cause delays due to stray electric fields. Now that circuits have become much denser and more complex, the magnetic field effects are starting to become significant as well, causing these so-called parasitic inductances. These effects become more profound as technologies get smaller that more accurate algorithms become necessary, yet the speed of them must remain the same. Typically these algorithms are very fast compared to other parts of the design flow, but the accuracy is becoming much worse. We desire an algorithm that can calculate the parasitic inductances within a circuit efficiently, necessitating both accuracy and speed We use an existing treecode algorithm from previous works provided by Professor Andrew J. Christlieb. We consider this an efficient algorithm in that it ensures the necessary accuracy we desire at reasonable computation speed.