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dc.contributor.authorDobson, Ianen_US
dc.contributor.authorLu, Limingen_US
dc.date.accessioned2007-07-13T19:31:25Z
dc.date.available2007-07-13T19:31:25Z
dc.date.issued1993en_US
dc.identifier.citationDobson, I., & Lu, L. (1993). New Methods For Computing A Closest Saddle Node Bifurcation And Worst Case Load Power Margin For Voltage. Ieee Transactions On Power Systems, 8(3), 905-913.en_US
dc.identifier.urihttp://digital.library.wisc.edu/1793/10856
dc.descriptionThis material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.format.extent1099115 bytes
dc.format.mimetypeapplication/pdfen_US
dc.format.mimetypeapplication/pdf
dc.publisherPubl by IEEE, Piscataway, NJ, USAen_US
dc.relation.ispartofhttp://www.ieee.org/en_US
dc.relation.ispartofhttp://ieeexplore.ieee.org/servlet/opac?punumber=59en_US
dc.rightsCopyright 1993 Institute of Electrical and Electronics Engineersen_US
dc.rights©20xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.titleNew methods for computing a closest saddle node bifurcation and worst case load power margin for voltageen_US
dc.identifier.doihttp://dx.doi.org/10.1109/59.260912en_US


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