Scheduling tests for VLSI systems under power constraints
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- Author(s)
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Chou, Richard M.; Saluja, Kewal K.; Agrawal, Vishwani D.
- Publisher
- IEEE, Piscataway, NJ, USA
- Citation
- Chou, R. M., Saluja, K. K., & Agrawal, V. D. (1997). Scheduling Tests For Vlsi Systems Under Power Constraints. Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, 5(2), 175-185.
- Date
- 1997
- Part of
- http://www.ieee.org/; http://ieeexplore.ieee.org/servlet/opac?punumber=92
- Description
- This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
- Permanent link
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http://digital.library.wisc.edu/1793/10318
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