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Yield-driven, false-path-aware clock skew scheduling

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Author(s)
Tsai, Jeng-Liang; Baik, Dong Hyun; Chen, Charlie Chung-Ping; Saluja, Kewal K.
Publisher
Institute of Electrical and Electronics Engineers Computer Society, Piscataway, NJ 08855-1331, United States
Citation
Tsai, J.L., Dong, B. Hyun, C., Charlie C.P., & Saluja, K. K. (2005). Yield Driven, False Path Aware Clock Skew Scheduling. Ieee Design And Test Of Computers, 22(3), 214-222.
Date
2005
Part of
http://www.ieee.org/; http://ieeexplore.ieee.org/servlet/opac?punumber=4069487
Description
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
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http://digital.library.wisc.edu/1793/10316 
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