Browse by Author

MINDS@UW Home >
Browse by Author

Browse by Author

Showing 1-20 of 20

Cache Memory Design Considerations to Support Languages with Dynamic Heap Allocation

Peng, Chih-Jui; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Data Memory Alternatives for Multiscalar Processors

Breach, Scott E; Vijaykumar, T N; Gopal, Sridhar; Smith, James E; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Design and Analysis of a Gracefully-Degrading Interleaved Memory System

Cheung, Kifung; Sohi, Gurindar S; Saluja, Kewal; Pradhan, Dhiraj (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
A Dynamic Approach to Improve the Accuracy of Data Speculation

Moshovos, Andreas I.; Breach, Scott E.; Vijaykumar, T.N.; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
The Effects of Faults in Cache Memories

Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Efficient Detection of all Pointer and Array Access Errors

Austin, Todd M; Breach, Scott E; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment

Chiang, Men-Chow; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Guarded Execution and Branch Prediction in Dynamic ILP Processors

Pnevmatikatos, Dionisios N; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
High-Bandwidth Data Memory Systems for Superscalar Processors

Sohi, Gurindar S; Franklin, Manoj (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study

Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Instruction Issue Logic for High Performance, Interruptible, Multiple Functional Unit, Pipelined Computers

Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Knapsack: A Zero-Cycle Memory Hierarchy Component

Austin, Todd M; Vijaykumar, TN; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Logical Data Skewing Schemes for Interleaved Memories in Vector Processors

Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
The Performance Potential of Multiple Functional Unit Processors

Pleszkun, Andrew R; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Restricted Fetch and \(*F Operations for Parallel Processing

Sohi, Gurindar S; Smith, James E; Goodman, James R (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Speculative Versioning Cache

Gopal, Sridhar; Vijaykumar, T N; Smith, James E; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Tetra: Evaluation of Serial Program Performance on Fine-Grain Parallel Processors

Austin, Todd M; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Tradeoffs in Instruction Format Design for Horizontal Architectures

Sohi, Gurindar S; Vajapeyam, Sriram (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
The TREEBus Architecture and Its Analysis

Jog, Rajeev; Sohi, Gurindar S; Vernon, Mary K (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)
Using Feedback to Control Tree Saturation in Multistage Interconnection Networks

Scott, Steven; Sohi, Gurindar S (University of Wisconsin-Madison Department of Computer Sciences; Mar 15, 2012)

Showing 1-20 of 20

Advanced Search

Browse

All of MINDS@UW
- Sitemap
- By date
- By author
- By title
- By subject

Deposit materials

About MINDS@UW