Browsing by Author "Hill, Mark D."
Now showing items 9-28 of 32
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Evaluating associativity in CPU caches
Hill, Mark D.; Smith, Alan Jay (1989) -
A "flight data recorder" for enabling full-system multiprocessor deterministic replay
Xu, Min; Bodik, Rastislav; Hill, Mark D. (Institute of Electrical and Electronics Engineers Computer Society, 2003) -
FreshCache: Statically and Dynamically Exploiting Dataless Ways
Swift, Michael M.; Hill, Mark D.; Hower, Derek R.; Basu, Arkaprava (2013-06-17)Last level caches (LLCs) account for a substantial fraction of the area and power budget in many modern processors. Two recent trends ? dwindling die yield that falls off sharply with larger chips and increasing static ... -
Implementing Fine-Grain Distributed Shared Memory on Commodity SMP Workstations
Schoinas, Ioannis; Falsafi, Babak; Hill, Mark D.; Larus, James R.; Lukas, Christopher E.; Mukherjee, Shubhendu S.; Reinhardt, Steven K.; Schnarr, Eric; Wood, David A. (University of Wisconsin-Madison Department of Computer Sciences, 1996) -
Interaction cost: For when event counts just don't add up
Fields, Brian A.; Bodik, Rastislav; Hill, Mark D.; Newburn, Chris J. (IEEE COMPUTER SOC, 2004) -
Karma: Scalable Deterministic Record-Replay
Basu, Arkaprava; Bobba, Jayaram; Hill, Mark D. (University of Wisconsin-Madison Department of Computer Sciences, 2010)Recent research in deterministic record-replayseeks to ease debugging, security, and fault tolerance on otherwise nondeterministic multicore systems. The important challenge of handling shared memory races (that can occur ... -
Making pointer-based data structures cache conscious
Chilimbi, Trishul M.; Hill, Mark D.; Larus, James R. (IEEE COMPUTER SOC, 2000) -
Multiprocessors should support simple memory-consistency models
Hill, Mark D. (IEEE Comp Soc, Los Alamitos, CA, USA, 1998) -
OS Support for Virtualizing Hardware Transactional Memory
Swift, Michael M.; Volos, Haris; Goyal, Neelam; Yen, Luke; Hill, Mark D.; Wood, David A. (University of Wisconsin-Madison Department of Computer Sciences, 2008)Transactional memory promises to simplify multithreaded programming. Hardware TM (HTM) implementations promise better performance by augmenting processors with transactional state. However, HTMs interact poorly with the ... -
Performance implications of tolerating cache faults
Pour, Andreas Farid; Hill, Mark D. (1993) -
Probabilistic Directed Writebacks for Exclusive Caches
Olson, Lena E.; Hill, Mark D. (2016-02-26)Energy is an increasingly important consideration in memory system design. Although caches can save energy in several ways, such as by decreasing execution time and reducing the number of main memory accesses, they also ... -
Programming Heterogeneous Computers and Improving Inter-Node Communication Across Xeon Phis
Feilbach, Chris; Sperling, Adam; Sifakis, Eftychios; Hill, Mark D. (2016-05-20)Scientific computing workloads are well suited to parallel accelerators such as GPGPUs and the Intel Xeon Phi. While these accelerators can provide greater performance than traditional CPUs due to their parallel architectures ... -
Revisiting Stack Caches for Energy Efficiency
Olson, Lena; Eckert, Yasuko; Manne, Srilatha; Hill, Mark D. (2014-12-15)With the growing focus on energy efficiency, it is important to find ways to reduce energy without sacrificing performance. The L1 data cache is a significant contributor to processor energy consumption. We advocate treating ... -
SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery
Sorin, Daniel J.; Martin, Milo M.K.; Hill, Mark D.; Wood, David A. (Institute of Electrical and Electronics Engineers Computer Society, 2002) -
Simulating a $2M commercial server on a $2K PC
Alameldeen, Alaa R.; Martin, Milo M.K.; Mauer, Carl J.; Moore, Kevin E.; Xu, Min; Hill, Mark D.; Wood, David A.; Sorin, Daniel J. (Institute of Electrical and Electronics Engineers Computer Society, 2003) -
Slack: Maximizing performance under technological constraints
Fields, Brian A.; Bodik, Rastislav; Hill, Mark D. (Institute of Electrical and Electronics Engineers Computer Society, 2002) -
Specifying and verifying a broadcast and a multicast snooping cache coherence protocol
Sorin, Daniel J.; Plakal, Manoj; Condon, Anne E.; Hill, Mark D.; Martin, Milo M.K.; Wood, David A. (Institute of Electrical and Electronics Engineers Computer Society, 2002) -
Thread-Level Transactional Memory
Moore, Kevin E.; Hill, Mark D.; Wood, David A. (University of Wisconsin-Madison Department of Computer Sciences, 2005)This paper presents thread-level transactional memory (TTM), a memory system interface that separates the semantics of transactions-atomicity, consistency, and isolation-from the implementation. By making transactions a ... -
Unified formalization of four shared-memory models
Adve, Sarita V.; Hill, Mark D. (1993) -
Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors
Martin, Milo M.K.; Harper, Pacia J.; Sorin, Daniel J.; Hill, Mark D.; Wood, David A. (Institute of Electrical and Electronics Engineers Computer Society, 2003)